Low Power CMOS Approximate Voting Architecture for Reliable Computing

Low Power CMOS Approximate Voting Architecture for Reliable Computing

AngličtinaMäkká väzbaTlač na objednávku
Sundaram, Kalaiselvi
LAP Lambert Academic Publishing
EAN: 9786139845651
Tlač na objednávku
Predpokladané dodanie vo štvrtok, 24. apríla 2025
37,88 €
Bežná cena: 42,09 €
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Podrobné informácie

Soft errors have a predominant role in the design of integrated electronic circuits. Modular Redundancy is a technique used to suppress the effects caused by soft error. In conventional Triple Modular Redundancy scheme, voter generates error if majority cannot be detected. Introducing approximations in the conventional schemes reduces the error probability. The book presents the design of approximate scheme for alleviating the soft error by combining Inexact Double Modular Redundancy and Approximate Triple Modular Redundancy. The Approximate TMR module overcomes this problem by mediating the output instead of generating error. The scheme is designed using Cadence EDA tool with 180nm technology. Parameter analysis revealed power of the approximate design is being reduced by 49.11% from the existing design.
EAN 9786139845651
ISBN 6139845653
Typ produktu Mäkká väzba
Vydavateľ LAP Lambert Academic Publishing
Stránky 56
Jazyk English
Rozmery 220 x 150 x 3
Autori Krishnasamy Natarajan, Vijeyakumar; Natarajan, Saravanakumar; Sundaram, Kalaiselvi
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